A network on a chip (NOC) is a novel integrated circuit architecture that applies a network-based architecture to a single chip to create a unique processing unit. A typical NOC includes a plurality of integrated processor (IP) blocks coupled to one another via the network. NOC processing units typically distribute (i.e., allocate) various parts of a job to different hardware threads of one or more IP blocks to be executed by the one or more IP blocks in the NOC processing unit. With the number of IP blocks in standard computer systems expected to rise, distributing tasks of a workload to hardware threads of the IP blocks has become increasingly demanding. In general, when distributing a workload, the status of hardware threads of IP blocks may be useful when determining whether to allocate a task to a particular IP block. Retrieving and accumulating thread status information, however, may be a processing resource expensive task in systems configured with large numbers of hardware threads.
A continuing need exists in the art for a manner of increasing the efficiency of workload distribution in computing systems including a plurality of interconnected integrated processor blocks.